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Electronic Colloquium on Computational Complexity

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REPORTS > KEYWORD > SYSTOLIC ARRAYS:
Reports tagged with systolic arrays:
TR23-186 | 28th November 2023
Ce Jin, Ryan Williams, Nathaniel Young

A VLSI Circuit Model Accounting For Wire Delay

Given the need for ever higher performance, and the failure of CPUs to keep providing single-threaded performance gains, engineers are increasingly turning to highly-parallel custom VLSI chips to implement expensive computations. In VLSI design, the gates and wires of a logical circuit are placed on a 2-dimensional chip with a ... more >>>




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