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Paper:

TR16-099 | 13th June 2016 12:29

Bounded Depth Circuits with Weighted Symmetric Gates: Satisfiability, Lower Bounds and Compression

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TR16-099
Authors: Takayuki Sakai, Kazuhisa Seto, Suguru Tamaki, Junichi Teruyama
Publication: 17th June 2016 16:19
Downloads: 340
Keywords: 


Abstract:

A Boolean function $f: \{0,1\}^n \to \{0,1\}$ is weighted symmetric if there exist a function $g: \mathbb{Z} \to \{0,1\}$ and integers $w_0, w_1, \ldots, w_n$ such that $f(x_1,\ldots,x_n) = g(w_0+\sum_{i=1}^n w_i x_i)$ holds.

In this paper, we present algorithms for the circuit satisfiability problem of bounded depth circuits with AND, OR, NOT gates and a limited number of weighted symmetric gates. Our algorithms run in time super-polynomially faster than $2^n$ even when the number of gates is super-polynomial and the maximum weight of symmetric gates is nearly exponential. With an additional trick, we give an algorithm for the maximum satisfiability problem that runs in time $poly(n^t) \cdot 2^{n-n^{1/O(t)}}$ for instances with $n$ variables, $O(n^t)$ clauses and arbitrary weights. To the best of our knowledge, this is the first moderately exponential time algorithm even for Max $2$SAT instances with arbitrary weights.

Through the analysis of our algorithms, we obtain average-case lower bounds and compression algorithms for such circuits and worst-case lower bounds for majority votes of such circuits, where all the lower bounds are against the generalized Andreev function. Our average-case lower bounds might be of independent interest in the sense that previous ones for similar circuits with arbitrary symmetric gates rely on communication complexity lower bounds while ours are based on the restriction method.



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